In conventional pass-transistor circuits, where the pass-transistor includes a gate, drain and source terminal, the gate and drain high logic levels are equal to the power supply voltage. Under these conditions the source high logic level is reduced by the MOS threshold voltage Vt. This results in decreasing the noise margin and speed of the pass-transistor stage. Moreover, when a load capacitance connected to the source is charged, the effective control voltage decreases from a maximum value to zero and the drain-to-source resistance increases from a minimum value to the infinity. This substantially increases the low-high delay of the pass-transistor stage. Attempts to increase speed by means of decreasing pass threshold leads to increasing the subthreshold leakage current, thereby increasing the power consumption. This also decreases the discharge time when operating in a dynamic mode.